參數(shù)資料
型號: MC68HC05T7B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 10/109頁
文件大小: 9008K
代理商: MC68HC05T7B
Multifunction Timer Module
Operation
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
Technical Data
MOTOROLA
Multifunction Timer Module
109
10.4 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage allows a timer interrupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system.
For information on the COP, refer to Section 8. Computer Operating
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Timer Status and Control Register
(TSCR)
Read:
TOF
RTIF
TOIE
RTIE
00
RT1
RT0
Write:
TOFR
RTIFR
Reset:
00
0
00
11
Timer Counter Register (TCR)
Read:
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Write:
Reset:
00
0
00
= Unimplemented
Figure 10-2. I/O Register Summary
Table 10-1. I/O Register Address Summary
Register:
TSCR
TCR
Address:
$0008
$0009
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