參數(shù)資料
型號： MC68HC05P9DWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 55/88頁
文件大?。?/td> 6557K
代理商： MC68HC05P9DWR2
7
MOTOROLA
7-4
MC68HC05E0
TIMERS
7.4
Control Registers for Timer A and Timer B
Timer A and Timer B are enabled/disabled via the CETA (Count Enable Timer A) and CETB (Count
Enable Timer B) control bits in the Timer Control Register ($000C).
CETA, CETB
1 (set)
–
Counter enabled
0 (clear) –
Counter disabled
Both timers generate a signal on overow which can be used to interrupt the processor. These
signals can be masked by the INTMA and INTMB bits in the Interrupt Control Register ($000E).
Timer Interrupt Flag and Acknowledge bits INTFA and INTFB indicate when a timer interrupt has
occurred and can be written to reset the timer interrupt logic.
INTMA, INTMB
1 (set)
–
Interrupts not masked
0 (clear) –
Interrupts masked
INTFA, INTF
1 (set)
–
Interrupt has occurred
0 (clear) –
Interrupt has not occurred
Writing a “0” to INTFA or INTFB acknowledges the interrupt and resets the interrupt signal for that
timer.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer control register
$000C
SC1
SC0
PITX
PITW
1
XROM CETB
CETA 0000 1100
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Interrupt control register
$000C
WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001
64
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