參數(shù)資料
型號(hào)： MC68HC05J5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 48/69頁(yè)
文件大?。?/td> 394K
代理商： MC68HC05J5P
GENERAL RELEASE SPECIFICATION
December 11, 1996
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05J5
8-4
REV 1.1
TOFR - Timer Overow Acknowledge
The TOFR is an acknowledge bit that resets the TOF ag bit. This bit is unaf-
fected by reset. Reading the TOFR will always return a logical zero.
1 =
Clears the TOF ag bit.
0 =
Does not clear the TOF ag bit.
RTIFR - Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF ag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
1 =
Clears the RTIF ag bit.
0 =
Does not clear the RTIF ag bit.
RT1:RT0 - Real Time Interrupt Rate Select
The RT0 and RT1 control bits select one of four taps for the Real Time Interrupt
circuit. Table 8-1 shows the available interrupt rates for two fOP values. Both the
RT0 and RT1 control bits are set by reset, selecting the lowest periodic rate and
therefore the maximum time in which to alter these bits if necessary. Care
should be taken when altering RT0 and RT1 if the time-out period is imminent
or uncertain. If the selected tap is modied during a cycle in which the counter
is switching, an RTIF could be missed or an additional one could be generated.
To avoid problems, the COP should be cleared just prior to changing RTI taps.
Table 8-1. RTI Rates and COP Reset Times
8.2
COP WATCHDOG TIMER
The COP (Computer Operating Properly) Watchdog Timer function is imple-
mented on this device by using the output of the RTI circuit and further dividing it
by eight. The minimum COP reset times are listed in Table 8-1. If the COP circuit
times out, an internal reset is generated and the reset vector is fetched. Prevent-
ing a COP time-out is done by writing a logical zero to bit 0 of address $07F0 as
shown in Figure 8-4. The COP register is shared with a Test ROM byte. This
address location is not affected by any reset signals. Reading this location will
return the Test ROM byte. When the COP is cleared, only the nal divide by eight
stage (output of the RTI) is cleared. The COP Watchdog Timer can be enabled/
disabled by a mask option.
RT1:RT0
1.000 MHz
2.000 MHz
00
32.768 ms
16.384 ms
01
65.536 ms
32.768 ms
10
131.072 ms
65.536 ms
11
RTI RATES AT fOP FREQ. SPECIFIED:
16.384 ms
8.192 ms
Divider
32768
65536
131072
16384
Divider
262144
524288
1048576
131072
1.000 MHz
2.000 MHz
262 ms
131 ms
524 ms
262 ms
1.059 s
524 ms
131 ms
66 ms
MIN. COP RESET AT fOP FREQ. SPECIFIED:
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