參數(shù)資料
型號(hào)： MC68HC05J5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 26/69頁(yè)
文件大小： 394K
代理商： MC68HC05J5P
GENERAL RELEASE SPECIFICATION
December 11, 1996
MOTOROLA
INTERRUPTS
MC68HC05J5
4-6
REV 1.1
IRQE - IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF ag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQF interrupt, that is, the IRQF ag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 =
The IRQF ag bit cannot generate an interrupt sequence.
4.4.3 Optional External Interrupts (PA0-PA3)
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins
if enabled by a single mask option. If enabled, the lower four bits of Port A can
activate the IRQ interrupt function, and the interrupt operation will be the same as
for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these
input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins
must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt
sources are also controlled by the IRQE enable bit.
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the output of the logic OR function with the PA0 to PA3 pins. The state of the
individual Port A pins can be checked by reading the appropriate Port A pins as
inputs.
NOTE
If enabled, the PA0 to PA3 and PA7 pins will cause an IRQ interrupt regardless of
whether these pins are congured as inputs or outputs.
4.4.4 Timer Interrupt (TIMER)
The TIMER interrupt is generated by the multi-function timer when either a timer
overow or a real time interrupt has occurred as described in Section 8. The
interrupt ags and enable bits for the Timer interrupts are located in the Timer
Control/Status Register (TCSR) located at $0008. The I-bit in the CCR must be
clear in order for the TIMER interrupt to be enabled. Either of these two interrupts
will vector to the same interrupt service routine located at the address specied by
the contents of memory locations $07F8 and $07F9.
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