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參數(shù)資料
| 型號： | MC68HC05J5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 39/69頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MC68HC05J5P |
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GENERAL RELEASE SPECIFICATION
December 11, 1996
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05J5
7-4
REV 1.1
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the internal IRQ input to the CPU. Therefore BIH and BIL cannot be used to
test the state of the lower four Port A input pins as a group nor that of PA7.
7.3
PORT B
Port B is a 6-bit bidirectional port which functions as shown in Figure 7-3. Each
Port B pin is controlled by the corresponding bits in a data direction register, a
data register, and a pull-down/up register. The Port B Data Register is located at
address $0001. The Port B Data Direction Register (DDRB) is located at address
$0005. The Port B Pull-down/up Register (PDURB) is located at address $0011.
Reset clears the DDRB and the PDURB. The Port B Data Register is unaffected
by reset.
PB1 and PB2 are open-drained type I/Os, capable of typically sinking 25mA
current each, at VOL 0.5V max.
For the 16-pin package, PB1 and PB2 are connected together to form the pin
labelled PB1 on the package. This PB1 pin will have a maximum sink current of
50mA if both PB1 and PB2 are written with the same value at the same write
cycle.
Figure 7-3. Port B I/O Circuitry
Write $0011
Read $0001
Write $0001
Read $0005
Write $0005
Internal HC05
Data Bus
100
A
Pull-down
Data
Register Bit
I/O
Pin
Output
Mask Option
(Software Pull-down/up Inhibit)
Reset
(RST)
Data Direction
Register Bit
Pull-down/up
Register Bit
VDD
100K
Pull-up
Note: each I/O port pin can have either Pull-up and pull-down device not both
PB1 and PB2 output drivers are of open-drained type
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