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| 型號(hào)： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 70/145頁 |
| 文件大小： | 673K |
| 代理商： | MC68HC05CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
CPU
MC68HC05CL48
3-2
REV 2.0
or non-arithmetic operations. The accumulator is unaffected by a reset of the
device.
3.1.2 Index Register (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
Indexed addressing
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU nds the operand address by adding the
index register contents to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU nds the operand address by adding the index register
contents to a 16-bit immediate value
The index register can also serve as an auxiliary accumulator for temporary
storage.The index register is unaffected by a reset of the device.
3.1.3 Stack Pointer (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register internally. In devices
with memory maps less than 64 kbytes the unimplemented upper address lines
are ignored. The stack pointer contains the address of the next free location on
the stack. During a reset or the reset stack pointer (RSP) instruction, the stack
pointer is set to $00FF. The stack pointer is then decremented as data is pushed
onto the stack and incremented as data is pulled from the stack.
When accessing memory, the ten most signicant bits are permanently set to
0000000011. The six least signicant register bits are appended to these ten xed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 ($40) locations. If 64 locations are exceeded, the
stack pointer wraps around and writes over the previously stored information. A
subroutine call occupies two locations on the stack, and an interrupt uses ve
locations.
3.1.4 Program Counter (PC)
The program counter shown in Figure 3-1 is a 16-bit register internally. In devices
with memory maps less than 64 Kbytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
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