參數(shù)資料
型號: MC68HC05CL48
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝: TQFP-112
文件頁數(shù): 138/145頁
文件大小: 673K
代理商: MC68HC05CL48
GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
CALLER-ID
MC68HC05CL48
11-8
REV 2.0
RDPW, Bit6 (Ring Detect Power Up)
This bit when set is used to enable ring detection. An interrupt will be generated
when a valid ring is detected and if the RDIE bit in the CLCSR1 register is set.
11.7.3 Control/Status Register 3 (CLCSR3)
CDOE, Bit-0
Carrier Detect Override Enable, when set this bit disables the carrier detect
module output and allows the user to force the carrier detect signal by writing a
zero to CDO, bit 0 in the CLCSR1 register.
RDOE, Bit-1
Ring Detect Override Enable, when set this bit disables the ring detect module
output and allows the user to force the ring detect signal by writing a zero to
RDO, bit 1 in the CLCSR1 register.
CDRF, Bit-2
Caller_ID data ready ag. This is set to ‘1’ when the 8-bit data is ready to be
read. Reading CDDR ($000E) clears this bit.
DRIE, Bit-3 (Data Ready Interrupt Enable)
1 =
Enable CDRF to cause an interrupt.
0 =
Disable CDRF from generating an interrupt.
CDRE, Bit-4 (Caller_ID Receiver Enable)
1 =
Enable Caller_ID 8-bit data receiver.
0 =
Disable Caller_ID 8-bit data receiver.
SDSL, Bit-7 (Serial Data Select)
0 =
Select cooked data to be routed to the Caller ID parallel data
receiver.
1 =
Select raw data to be routed to the Caller ID parallel data receiver.
76543210
CLCSR3
$000C
READ
SDSL
CDRE
DRIE
CDRF
RDOE
CDOE
WRITE
RESET
0
U
0000
U = UNAFFECTED
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