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| 型號： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 100/145頁 |
| 文件大小： | 673K |
| 代理商： | MC68HC05CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
TIMER
MC68HC05CL48
8-6
REV 2.0
The 16-bit output compare register 1 is made up of two 8-bit registers at locations
$15 (MSB) and $16 (LSB). The output compare register contents are compared
with the contents of the free-running counter once every four internal processor
clock cycles. If a match is found, the corresponding output compare ag OC1F (bit
5 of timer status register $12) is set.
The output compare register values should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany
a successful output compare provided the corresponding interrupt enable bit
OC1IE (bit 5 of timer control register $11) is set.
After a processor write cycle to the output compare register containing the MSB
($15), the output compare function is inhibited until the LSB ($16) is also written.
The user must write both bytes (locations) if the MSB is written rst. A write made
only to the LSB ($16) will not inhibit the compare function. The free-running
counter is updated every four internal bus clock cycles. The minimum time
required to update the output compare register is a function of the program rather
than the internal hardware.
The processor can write to either byte of the output compare register without
affecting the other byte.
Because the output compare ag OC1F and the output compare register 1 are
undetermined at power on, and are not affected by external reset, care must be
exercised when initializing the output compare function. The following procedure
is recommended:
1.
Write the high byte to the compare register 1 to inhibit further compares
until the low byte is written.
2.
Read the status register to arm the OC1F if it is already set.
3.
Write the output compare register 1 low byte to enable the output
compare 1 function with ag clear.
The purpose of this procedure is to prevent the OC1F bit from being set between
the time it is read and the write to the corresponding output compare register.
76543210
OC1L
$0016
READ
OC1:7
OC1:6
OC1:5
OC1:4
OC1:3
OC1:2
OC1:1
OC1:0
WRITE
RESET
UUUUUUUU
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