參數(shù)資料
型號(hào)： MC68HC05C9AP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 30/162頁
文件大小： 1093K
代理商： MC68HC05C9AP
Electrical Specifications
5.0-Volt DC Electrical Characteristics
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Electrical Specifications
125
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
12.6 5.0-Volt DC Electrical Characteristics
Characteristic(1) (2)
Symbol
Min
Typ
Max
Unit
Output voltage
ILoad = 10.0 A
ILoad = –10.0 A
VOL
VOH
—
VDD–0.1
—
0.1
—
V
Output high voltage
(ILoad = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
(ILoad = –1.6 mA) PD5–PD1
(ILoad = –5.0 mA) PC7
VOH
VDD–0.8
—
V
Output low voltage
(ILoad = 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD7, PD5–PD0, TCMP
(ILoad = 10 mA) PC7
VOL
—
0.4
V
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7
× VDD
—
VDD
V
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2
× VDD
V
Supply current (4.5–5.5 Vdc @ fOP = 2.1 MHz)
Run(3)
Wait(4)
Stop(5)
25
°C
0 to 70
°C
–40 to +125
°C
IDD
—
3.5
1.0
2.0
7.0
5.25
3.25
20.0
40.0
50.0
mA
A
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
1.0
10
A
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
IIn
—
0.5
1
A
Input pullup current(6)
PB7–PB0 (with pullup)
IIn
5
—
60
A
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
COut
CIn
—
12
8
pF
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +125°C, unless otherwise noted
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25
°C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD,
all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD –0.2 V; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected
linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V
6. Input pullup current measured with VIL = 0.2 V
相關(guān)PDF資料
PDF描述
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