
Serial Peripheral Interface (SPI)
SPI Registers
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Serial Peripheral Interface (SPI)
99
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
SPR1 and SPR0 — SPI Clock Rate Select Bits
These read/write bits select one of four master mode serial clock
rates, as shown in Table 10-1. They have no effect in slave mode.
10.6.2 Serial Peripheral Status Register
The SPI status register (SPSR), shown in Figure 10-5, contains flags to
signal these conditions:
SPI transmission complete
Write collision
Mode fault
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
Table 10-1. SPI Clock Rate Selection
SPR1 and SPR0
SPI Clock Rate
0 0
Internal clock
÷ 2
0 1
Internal clock
÷ 4
1 0
Internal clock
÷ 16
1 1
Internal clock
÷ 32
Address:
$000B
Bit 7
6
54321
Bit 0
Read:
SPIF
WCOL
0
MODF
0000
Write:
Reset:
00
000000
= Unimplemented
Figure 10-5. SPI Status Register