參數(shù)資料
型號: MC68HC05C9AP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 106/162頁
文件大?。?/td> 1093K
代理商: MC68HC05C9AP
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Resets
Advance Information
MC68HC05C9A Rev. 5.0
48
Resets
MOTOROLA
A reset immediately stops the operation of the instruction being
executed, initializes some control bits, and loads the program counter
with a user-defined reset vector address. Figure 5-1 is a block diagram
of the reset sources.
Figure 5-1. Reset Sources
5.3 Power-On Reset (POR)
A power-on reset (POR) occurs when a positive transition is detected on
VDD. The power-on reset is strictly for power turn-on conditions and
should not be used to detect a drop in the power supply voltage. There
is a 4064 internal processor clock cycle (tCYC) oscillator stabilization
delay after the oscillator becomes active. The RESET pin will output a
logic 0 during the 4064-cycle delay. If the RESET pin is low after the end
of this 4064-cycle delay, the MCU will remain in the reset condition until
RESET is driven high externally.
VDD
RESET
LATCH
POWER-ON RESET
D
INTERNAL CLOCK
R
RST
TO CPU AND
SUBSYSTEMS
Q
STOP
CLOCK MONITOR
COP WATCHDOG
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