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| 型號(hào)： | MC68HC05C9AMB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SHRINK, PLASTIC, DIP-42 |
| 文件頁(yè)數(shù)： | 83/124頁(yè) |
| 文件大?。?/td> | 774K |
| 代理商： | MC68HC05C9AMB |
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SCI I/O Registers
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
61
RIE — Receiver Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the RDRF flag or the OR flag becomes set.
Resets clear the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Resets clear the
ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the PD1/TDO pin. Resets clear the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver
interrupts but does not affect the receiver interrupt flags. Resets clear the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears
the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines
whether an idle input or an address mark brings the receiver out of standby state. Reset clears the
RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of
logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears
the SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
9.11.4 SCI Status Register
The SCI status register (SCSR), shown in Figure 9-11, contains flags to signal these conditions:
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data SCDR complete
Receiver input idle
Noisy data
Framing error
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68HC05C9AMFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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| MC68HC05C9AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05C9CP | 制造商:Motorola Inc 功能描述:IC UP HCMOS 68HC05C9CP DIP40 0 |
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