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| 型號(hào)： | MC68HC05C9AMB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SHRINK, PLASTIC, DIP-42 |
| 文件頁(yè)數(shù)： | 62/124頁(yè) |
| 文件大小： | 774K |
| 代理商： | MC68HC05C9AMB |
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Input/Output Ports
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
42
Freescale Semiconductor
7.3 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register
(DDR) is at $0005. The contents of the port B data register are indeterminate at initial powerup and must
be initialized by user software. Reset does not affect the data registers, but clears the data direction
registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port pin
to output mode. Each of the port B pins has an optional external interrupt capability that can be enabled
by mask option.
The interrupt option also enables a pullup device when the pin is configured as an input. The edge or
edge- and level-sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be
taken when using port B pins that have the pullup enabled. Before switching from an output to an input,
the data should be preconditioned to a 1 to prevent an interrupt from occurring. The port B logic is shown
in Figure 7-2.
7.4 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register
(DDR) is at $0006. The contents of the port C data register are indeterminate at initial powerup and must
be initialized by user software. Reset does not affect the data registers, but clears the data direction
registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to
output mode. PC7 has a high current sink and source capability. Figure 7-1 is also applicable to port C.
7.5 Port D
Port D is a 7-bit bidirectional port. Four of its pins are shared with the SPI subsystem and two more are
shared with the SCI subsystem. The port D data register is at $0003 and the data direction register is at
$0007. The contents of the port D data register are indeterminate at initial powerup and must be initialized
by user software. During reset all seven bits become valid input ports because the DDR bits are cleared
and the special function output drivers associated with the SCI and SPI subsystems are disabled, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode.
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相關(guān)代理商/技術(shù)參數(shù) |
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