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參數(shù)資料
| 型號： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 32/58頁 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 32
MOTOROLA
Section 5: Input/Output Ports
MC68HC05C5 Specification Rev. 1.2
registers, thereby returning the ports to inputs.
Writing a 1 to a DDR bit sets the
corresponding port bit to output mode.
5.5
INPUT/OUTPUT PROGRAMMING
Port pins may be programmed as inputs or outputs under software control. The direction
of the pins is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any port pin is configured as an
output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if
its corresponding DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data
direction registers are capable of being written to or read by the processor. During the
programmed output state, a read of the data register actually reads the value of the output
data latch and not the I/O pin. Refer to Table 5-1 and Figure 5-1.
Table 5-1: I/O Pin Functions
R/W
0
1
DDR
0
1
0
1
I/O Pin Function
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output of the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.
R/W is an internal signal.
Data Direction
Register Bit
Latched Output
Data Bit
I/O
Pin
Input
Register
Bit
Input
I/O
Output
Internal
HC05
Connections
Figure 5-1: Port I/O Circuitry
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