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參數(shù)資料
| 型號(hào)： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 24/58頁 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 24
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
4.4.2
RESET PIN
The MCU is reset when a logic zero is applied to the RESET input for a period of one and
one-half machine cycles (t
CYC
).
4.4.3
COMPUTER OPERATING PROPERLY (COP) RESET
The MCU contains a watchdog timer that automatically times out if not reset (cleared)
within a specific time by a program reset sequence. If the COP watchdog timer is allowed
to time-out, an internal reset is generated to reset the MCU. Because the internal RESET
signal is used, the MCU comes out of a COP reset in the same operating mode it was in
when the COP time-out was generated.
The COP reset function is enabled or disabled by a mask option.
Refer to SECTION 8 COMPUTER OPERATING PROPERLY for more information on the
COP Watchdog timer.
4.5
INTERRUPTS
The MCU can be interrupted three different ways: by the two maskable hardware
interrupts (IRQ and timer) and the nonmaskable software interrupt instruction (SWI).
Interrupts cause the processor to save register contents on the stack and to set the
interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the
register contents to be recovered from the stack and normal processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be
halted, but are considered pending until the current instruction is complete.
NOTE:
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all pending hardware
interrupts. If interrupts are not masked (CCR I bit clear) and if the corresponding interrupt
enable bit is set, the processor proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end of an instruction
execution, the external interrupt is serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
Table 4-1 lists vector addresses for all interrupts including reset.
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