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MOTOROLA
MC68HC05C5 Specification Release 1.2
TABLE OF CONTENTS
SECTION 1
INTRODUCTION .............................................................. 1
1.1
GENERAL...................................................................................1
1.2
FEATURES.................................................................................1
1.3
MASK OPTIONS ........................................................................2
1.4
SIGNAL DESCRIPTION .............................................................3
1.4.1
VDD AND VSS ........................................................................3
1.4.2
PE..........................................................................................3
1.4.3
IRQ ........................................................................................3
1.4.4
OSC1 AND OSC2 .................................................................3
1.4.5
RESET ..................................................................................3
1.4.6
TCAP .....................................................................................3
1.4.7
PA0-PA7................................................................................3
1.4.8
PB0-PB7................................................................................4
1.4.9
PC0-PC7 ...............................................................................4
1.4.10
PD0-PD7 ...............................................................................4
SECTION 2
OPERATING MODES ...................................................... 5
2.1
SINGLE-CHIP MODE .................................................................5
2.2
SELF-CHECK MODE .................................................................6
SECTION 3
MEMORY ......................................................................... 9
3.1
ROM .........................................................................................11
3.2
RAM ..........................................................................................11
3.3
EEPROM ..................................................................................11
3.3.1
PROGRAMMING REGISTER $1C .....................................11
3.3.2
PROGRAMMING/ERASING PROCEDURES .....................13
SECTION 4
CPU CORE..................................................................... 15
4.1
REGISTERS .............................................................................15
4.1.1
ACCUMULATOR (A) ...........................................................15
4.1.2
INDEX REGISTER (X) ........................................................16
4.1.3
PROGRAM COUNTER (PC)...............................................16
4.1.4
STACK POINTER (SP) .......................................................16
4.1.5
CONDITION CODE REGISTER (CCR) ..............................16
4.2
INSTRUCTION SET .................................................................17
4.2.1
REGISTER/MEMORY INSTRUCTIONS .............................17
4.2.2
READ-MODIFY-WRITE INSTRUCTIONS ..........................18
4.2.3
BRANCH INSTRUCTIONS .................................................19
4.2.4
BIT MANIPULATION INSTRUCTIONS ...............................20
4.2.5
CONTROL INSTRUCTIONS ...............................................20
4.3
ADDRESSING MODES ............................................................21
4.3.1
IMMEDIATE ........................................................................21
4.3.2
DIRECT ...............................................................................21