參數(shù)資料
型號(hào): MC68HC05BD3P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁(yè)數(shù): 74/112頁(yè)
文件大小: 864K
代理商: MC68HC05BD3P
MOTOROLA
8-4
MC68HC05BD3
SYNC SIGNAL PROCESSOR
8
8.1.3
Free-running Pseudo Sync Signal Generator
If either HSYNC or VSYNC is absent, a free-running sync signal generator will be enabled. It
generates a pseudo vertical sync at 63.5Hz (1/(tcyc x 31488)) and a pseudo horizontal sync at
either 48.8KHz (1/(tCYC x 41)) or 62.5KHz (1/(tCYC x 32)), depending on the status of FOUT. This
set of free running sync signals replaces the inactive sync signals at the inputs and will be fed to
the VTTL and HTTL pins if the pins are selected for VTTL and HTTL function.
8.1.4
Sync Separation
Figure 8-3 is a block diagram of the Sync Separator which includes the duration counters for the
high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold
the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse
separation, a comparator, and a sync pulse insertion circuit.
The Low pulse duration counter examines the low pulse width of the incoming composite sync
signal. If it is within the horizontal sync pulse limit (8
s or 16 t
CYC), a horizontal sync pulse is
detected and the horizontal sync pulse counter is advanced. If the low pulse is wider than the limit,
Figure 8-3 Sync Separator
Sync separation logic
Sync insertion circuit
Comparator
Low pulse duration counter
High pulse duration counter
Horizontal Sync Register
Horizontal sync pulse counter
CLK
HSYNC
load
reset
count
in
out
equal
Hsync
Vsync
nish
(After polarity correction)
TPG
62
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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