參數(shù)資料
型號(hào)： MC68HC05BD3P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 30/112頁
文件大小： 864K
代理商： MC68HC05BD3P
MOTOROLA
2-4
MC68HC05BD3
PIN DESCRIPTION AND I/O PORTS
2
2.3.3
Port C
Port C is an 8-bit bidirectional port which shares pins with PWM and SSP subsystem. See
Section 6 for a detailed description of PWM and Section 8 for a detailed description of SSP. These
pins are congured to PWM output when the corresponding bits in the Conguration register 1 are
set, except PC6 and PC7. PC6 and PC7 are congured to SSP outputs when the corresponding
bits in the Conguration register 2 are set. The Port C data register is at $02 and the data direction
register (DDR) is at $06. Reset does not affect the data register, but clears the data direction
register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding
port bit to output mode.
2.3.4
Port D
Port D is a 2-bit bidirectional port which shares pins with M-Bus subsystem. See Section 7 for a
detailed description of M-Bus. These pins are congured to the corresponding functions when the
corresponding bits in the Conguration register 2 are set. They are +5V open-drain I/O pins when
used as M-Bus I/O. The Port D data register is at $03 and the data direction register (DDR) is at
$07. Reset does not affect the data register, yet clears the data direction register, thereby returning
the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.5
Input/Output Programming
Bidirectional port lines may be programmed as an input or an output under software control. The
direction of the pins is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is congured as an output if
its corresponding DDR bit is set. A pin is congured as an input if its corresponding DDR bit is
cleared.
During Reset, all DDRs are cleared, which congure all port pins as inputs. The data direction
registers are capable of being written to or read by the processor. During the programmed output
state, a read of the data register actually reads the value of the output data latch and not the I/O
pin.
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
TPG
22
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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