MC68HC05B6
Rev. 4
MOTOROLA
ix
LIST OF FIGURES
Figure
Number
Page
Number
TITLE
LIST OF FIGURES
1-1
2-1
2-2
2-3
2-4
2-5
3-1
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
7-1
7-2
7-3
8-1
8-2
9-1
9-2
9-3
MC68HC05B6 block diagram.............................................................................1–3
MC68HC05B6 ‘load program in RAM and execute’ schematic diagram.............2–3
MC68HC05B6 ‘jump to any address’ schematic diagram...................................2–5
STOP and WAIT flowcharts................................................................................2–7
Slow mode divider block diagram.......................................................................2–9
Oscillator connections ......................................................................................2–12
Memory map of the MC68HC05B6 ....................................................................3–2
Standard I/O port structure.................................................................................4–2
ECLK timing diagram..........................................................................................4–3
Port logic levels...................................................................................................4–6
16-bit programmable timer block diagram ..........................................................5–2
Timer state timing diagram for reset.................................................................5–13
Timer state timing diagram for input capture....................................................5–13
Timer state timing diagram for output compare................................................5–14
Timer state timing diagram for timer overflow...................................................5–14
Serial communications interface block diagram .................................................6–2
SCI rate generator division.................................................................................6–4
Data format.........................................................................................................6–5
SCI examples of start bit sampling technique ....................................................6–7
SCI sampling technique used on all bits.............................................................6–7
Artificial start following a framing error ...............................................................6–8
SCI start bit following a break.............................................................................6–8
SCI example of synchronous and asynchronous transmission..........................6–9
SCI data clock timing diagram (M=0) ...............................................................6–12
SCI data clock timing diagram (M=1) ...............................................................6–13
PLM system block diagram.................................................................................7–1
PLM output waveform examples.........................................................................7–2
PLM clock selection............................................................................................7–4
A/D converter block diagram ..............................................................................8–2
Electrical model of an A/D input pin....................................................................8–6
Reset timing diagram..........................................................................................9–1
Watchdog system block diagram........................................................................9–3
Interrupt flow chart..............................................................................................9–8
TPG