MOTOROLA
iv
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TABLE OF CONTENTS
7
PULSE LENGTH D/A CONVERTERS
7.1
7.2
7.3
7.4
Miscellaneous register.......................................................................................7–3
PLM clock selection...........................................................................................7–4
PLM during STOP mode ...................................................................................7–4
PLM during WAIT mode ....................................................................................7–4
8
ANALOG TO DIGITAL CONVERTER
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
A/D converter operation.....................................................................................8–1
A/D registers......................................................................................................8–3
Port D data register (PORTD)......................................................................8–3
A/D result data register (ADDATA)...............................................................8–3
A/D status/control register (ADSTAT)...........................................................8–4
A/D converter during STOP mode.....................................................................8–6
A/D converter during WAIT mode......................................................................8–6
Port D analog input............................................................................................8–6
9
RESETS AND INTERRUPTS
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.4.1
9.1.4.2
9.1.5
9.2
9.2.1
9.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.4
Resets ...............................................................................................................9–1
Power-on reset.............................................................................................9–2
Miscellaneous register................................................................................9–2
RESET pin...................................................................................................9–3
Computer operating properly (COP) watchdog reset ..................................9–3
COP watchdog during STOP mode .......................................................9–4
COP watchdog during WAIT mode ........................................................9–4
Functions affected by reset..........................................................................9–5
Interrupts ...........................................................................................................9–6
Interrupt priorities.........................................................................................9–6
Nonmaskable software interrupt (SWI)........................................................9–6
Maskable hardware interrupts......................................................................9–7
External interrupt (IRQ)..........................................................................9–7
Miscellaneous register ..........................................................................9–9
Timer interrupts....................................................................................9–10
Serial communications interface (SCI) interrupts.................................9–10
Hardware controlled interrupt sequence....................................................9–11
TPG