參數(shù)資料
型號(hào)： MC68C912B32FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-Bit Microcontroller
中文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 79/128頁
文件大?。?/td> 748K
代理商： MC68C912B32FU8
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
79
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value
of the free-running counter when a defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to these registers have no meaning
or effect during input capture. All timer input capture/output compare registers are reset to $0000.
Read or write anytime.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
PAEN is independent from TEN.
PAMOD — Pulse Accumulator Mode
0 = Event counter mode
1 = Gated time accumulation mode
TC3
— Timer Input Capture/Output Compare Register 3
$0096–$0097
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC4
— Timer Input Capture/Output Compare Register 4
$0098–$0099
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC5
— Timer Input Capture/Output Compare Register 5
$009A–$009B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC6
— Timer Input Capture/Output Compare Register 6
$009C–$009D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC7
— Timer Input Capture/Output Compare Register 7
$009E–$009F
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
PACTL
— Pulse Accumulator Control Register
$00A0
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
RESET:
0
0
0
0
0
0
0
0
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