參數(shù)資料
型號(hào)： MC68C912B32FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-Bit Microcontroller
中文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 6/128頁
文件大小： 748K
代理商： MC68C912B32FU8
MOTOROLA
6
MC68HC912B32
MC68HC912B32TS/D
2 Central Processing Unit
The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal reg-
isters (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset
of the M68HC11instruction set. The CPU12 allows instructions with odd byte counts, including many
single-byte instructions. This provides efficient use of ROM space. An instruction queue buffers pro-
gram information so the CPU always has immediate access to at least three bytes of machine code at
the start of every instruction. The CPU12 also offers an extensive set of indexed addressing capabilities.
2.1 Programming Model
CPU12 registers are an integral part of the CPU and are not addressed as if they were memory loca-
tions.
Figure 2 Programming Model
Accumulators
arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8-
bit accumulators as a 16-bit double accumulator (accumulator D).
A and B are general-purpose 8-bit accumulators used to hold operands and results of
Index registers
contents of a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an ac-
cumulator to form the effective address of the operand to be used in the instruction.
X and Y are used for indexed addressing mode. In the indexed addressing mode, the
Stack pointer
stack that is used to save system context during subroutine calls and interrupts, and can also be used
for temporary storage of data. The stack pointer can also be used in all indexed addressing modes.
(SP) points to the last stack location used. The CPU12 supports an automatic program
Program counter
program counter can be used in all indexed addressing modes except auto-increment/decrement.
is a 16-bit register that holds the address of the next instruction to be executed. The
Condition Code Register
STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow
(C). The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow
for branching based on the results of a previous operation.
(CCR) contains five status indicators, two interrupt masking bits, and a
7
15
15
15
15
15
D
IX
IY
SP
PC
A
B
N
S X H
I
Z V C
0
0
0
0
0
0
7
0
CONDITION CODE REGISTER
8-BIT ACCUMULATORS A & B
OR
16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
HC12 PROG MODEL
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