參數(shù)資料
型號(hào): MC56F8345VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 56F8345 16-bit Hybrid Controller
中文描述: 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝: 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù): 99/148頁
文件大小: 1420K
代理商: MC56F8345VFG60
Register Descriptions
56F8345 Technical Data
Preliminary
99
6.5.2.5
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be
cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while
writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset
was due to a Power-On Reset.
Power-On Reset (POR)—Bit 2
6.5.2.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 1–0
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1,
SIM_SCR2, and SIM_SCR3)
Only SIM_SCR0 is shown in this section. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical
in functionality.
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
6.5.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and
is intended for use by a software developer to contain data that will be unaffected by the other reset
sources (RESET pin, software reset, and COP reset).
Software Control Data 1 (FIELD)—Bits 15–0
6.5.4
This read-only register displays the most significant half of the JTAG ID for the chip. This register
reads $01F4.
Most Significant Half of JTAG ID (SIM_MSH_ID)
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FIELD
Write
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Write
RESET
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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