參數(shù)資料
型號: MC56F8345VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8345 16-bit Hybrid Controller
中文描述: 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝: 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù): 111/148頁
文件大小: 1420K
代理商: MC56F8345VFG60
Operation with Security Enabled
56F8345 Technical Data
Preliminary
111
Part 7 Security Features
The 56F8345 offers security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The 56F8345’s Flash security consists of several
hardware interlocks that block the means by which an unauthorized user could gain access to the
Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s
code that dumps the contents of the internal program, as this code would defeat the purpose of
security. At the same time, the user may also wish to put a “backdoor” in his program. As an
example, the user downloads a security key through the SCI, allowing access to a programming
routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8345 can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of
the FM array. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security.
Refer to the Flash Memory section in the
56F8300 Peripheral User Manual
for the state of the
security bytes and the resulting state of security. When Flash security mode is enabled in
accordance with the method described in the Flash Memory module specification, the 56F8345
will disable the core EOnCE debug capabilities. Normal program execution is otherwise
unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8345 has several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be
compromised and read without explicit user permission. Methods to block these are outlined in the
next subsections.
7.2.1
At boot time, the SIM determines in which functional modes the 56F8345 will operate. These are:
Forced Operating Mode Selection
Unsecured Mode
Secure Mode (EOnCE disabled)
When Flash security is enabled as described in the Flash Memory module specification, the
56F8345 will disable the EOnCE debug interface.
7.2.2
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8345 boots, the
chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability
and access to the ID register.
Disabling EOnCE Access
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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