參數(shù)資料
型號: MC56F8345VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8345 16-bit Hybrid Controller
中文描述: 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝: 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù): 87/148頁
文件大?。?/td> 1420K
代理商: MC56F8345VFG60
Register Descriptions
56F8345 Technical Data
Preliminary
87
5.6.11.1 Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—
Bits 12–0
The contents of this register determine the location of the Vector Address Table. The value in this
register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower
eight bits are determined based upon the highest-priority interrupt. They are then appended onto
VBA before presenting the full interrupt address to the 56800E core; see
Section 5.3.1 Normal
Interrupt Handling
for details.
5.6.12
Fast Interrupt 0 Match Register (FIM0)
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a
service routine based on values in the Fast Interrupt Vector Address registers without having to go
to a jump table first; see
Section 5.3.3 Fast Interrupt Handling
. IRQs used as fast interrupts
must
be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other
priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of
their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has
priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
Table 4-5
.
5.6.13
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with
FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FAST INTERRUPT 0
VECTOR ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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