參數(shù)資料
型號: MC56F8335MFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數(shù): 24/164頁
文件大?。?/td> 871K
代理商: MC56F8335MFGE
56F8335 Technical Data, Rev. 5
12
Freescale Semiconductor
Preliminary
1.5 Product Documentation
The documents listed in Table 1-3 are required for a complete description and proper design with the
56F8335 and 56F8135 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor
sales
offices,
Freescale
Literature
Distribution
Centers,
or
online
at
http://www.freescale.com.
Table 1-2 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0]
Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are
used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on
cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
Secondary Data Memory Interface
xdb2_m[15:0]
Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing
only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as
the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
Table 1-3 Chip Documentation
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E family architecture,
16-bit hybrid controller core processor, and the
instruction set
DSP56800ERM
56F8300 Peripheral User
Manual
Detailed description of peripherals of the 56F8300
family of devices
MC56F8300UM
56F8300 SCI/CAN
Bootloader User Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
MC56F83xxBLUM
56F8335/56F8135
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
device specific peripheral information and package
descriptions (this document)
MC56F8335
Errata
Details any chip issues that might be present
MC56F8335E
MC56F8135E
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