參數資料
型號： MC56F8335MFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數字信號處理
英文描述： 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝： ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數： 101/164頁
文件大?。?/td> 871K
代理商： MC56F8335MFGE
Data Map
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
41
Preliminary
4.4 Data Map
Note: Data Flash is NOT available on the 56F8135 device.
PWMA
80
0-2
P:$A0
PWM A Fault
core
81
- 1
P:$A2
SW Interrupt LP
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
Table 4-6 Data Memory Map1, 2
1. Information in shaded areas not applicable to 56F8335/56F8135.
2. All addresses are 16-bit Word addresses, not byte addresses.
Begin/End Address
EX = 03
3. In the Operation Mode Register.
EX = 14
4. Setting EX = 1 is not recommended in the 56F8335/56F8135, since the EMI is not functional in this package.
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 2000
External Memory
X:$00 1FFF
X:$00 1000
On-Chip Data Flash
8KB
X:$00 0FFF
X:$00 0000
On-Chip Data RAM
8KB5
5. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations.
Table 4-5 Interrupt Vector Table Contents1 (Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
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