參數(shù)資料
型號(hào)： MC56F8335MFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝： ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數(shù)： 149/164頁
文件大?。?/td> 871K
代理商： MC56F8335MFGE
Register Descriptions
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
85
Preliminary
5.6.7
Interrupt Priority Register 6 (IPR6)
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.3
Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TMRC0
IPL
TMRD3
IPL
TMRD2
IPL
TMRD1
IPL
TMRD0
IPL
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
Write
RESET
00000
0000000
0000
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