參數(shù)資料
型號： MC56F8014VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 90/124頁
文件大小： 0K
描述： IC DIGITAL SIGNAL CTRLR 32-LQFP
標準包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
56F8014 Technical Data, Rev. 11
68
Freescale Semiconductor
(COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts
executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.4
External Reset (EXTR)—Bit 3
When set, this bit indicates that the previous system reset was caused by an external reset. It will only be
set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted.
6.3.2.5
Power-On Reset (POR)—Bit 2
This bit is set during a Power-On Reset.
6.3.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.3
SIM Software Control Registers (SIM_SWC0, SIM_SWC1,
SIM_SWC2, and SIM_SWC3)
Only SIM_SWC0 is shown in this section. SIM_SWC1, SIM_SWC2, and SIM_SWC3 are identical in
functionality.
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0)
6.3.3.1
Software Control Data 0 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.3.4
Most Significant Half of JTAG ID (SIM_MSHID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Software Control Data 0
Write
RESET
0
000
0
000
0
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
Write
RESET
0
1
111
1
001
0
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