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參數(shù)資料
| 型號(hào)： | MC56F8014VFAE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 89/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL SIGNAL CTRLR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 16KB（8K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤 |
| 配用： | DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014 |
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Register Descriptions
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
67
6.3.1.11
Stop Disable (STOP_DISABLE[1:0])—Bits 3–2
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.12
Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
6.3.2
SIM Reset Status Register (SIM_RSTAT)
This register is updated upon any system reset and indicates the cause of the most recent reset. It also
controls whether the COP reset vector or regular reset vector in the vector table is used. This register is
asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is
synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only
one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the
highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR,
COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the
external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted.
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
6.3.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.
6.3.2.2
Software Reset (SWR)—Bit 5
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SW RST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also
occurred.
6.3.2.3
COP Reset (COPR)—Bit 4
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
SWR
COPR
EXTR
POR
0
Write
RESET
0
00
0
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