參數(shù)資料
型號： MC56F8014VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 39/124頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTRLR 32-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
56F8014 Signal Pins
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
21
TDO
(GPIOD1)
31
Output
Input/
Output
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDO.
GPIOB0
(SCLK)
(SCL3)
21
Input/
Output
Input/
Output
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SPI Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Serial Data — This pin serves as the I2C serial clock.
After reset, the default state is GPIOB0. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
3. This signal is also brought out on the GPIOB7 pin.
GPIOB1
(SS)
(SDA4)
1
Input/
Output
Input
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SPI Slave Select — SS is used in slave mode to indicate to the SPI
module that the current transfer is to be received.
Serial Clock — This pin serves as the I2C serial data line.
After reset, the default state is GPIOB1. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
4. This signal is also brought out on the GPIOB6 pin.
Return to Table 2-2
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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