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參數(shù)資料
| 型號(hào)： | MC56F8014VFAE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 100/124頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DIGITAL SIGNAL CTRLR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 16KB（8K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤(pán) |
| 配用： | DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014 |
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Clock Generation Overview
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
77
Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.10.3
Input/Output Short Address Location (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.4 Clock Generation Overview
The SIM uses master clocks, 2X system clock at a maximum of 64 MHz, from the OCCS module to
produce the peripheral and system (core and memory) clocks at a maximum of 32 MHz. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. The high speed
peripheral clock input from OCCS operates at three times the system clock for PWM and Quad Timer
module at a maximum of 96 MHz.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC).
When selected, the relaxation oscillator can be operated at full speed (8 MHz), standby speed (200 kHz),
or powered down. An 8 MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide
a variety of high speed clock rates. Either the postscaled PLL output or the input clock of the PLL signal
can be selected to produce the master clocks to the SIM. When the PLL is not selected, the high speed
peripheral clock is disabled and the 2x system clock is the input clock from either the internal relaxation
oscillator or from an external clock source.
In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral
Reference Manual for further details.
6.5 Power-Down Modes
The 56F8014 operates in one of five Power-Down modes, as shown in Table 6-3
.
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
ISAL[21:6]
Write
RESET
11111
1
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Core and memory
clocks disabled
Peripheral clocks
enabled
Device is fully functional
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| MC56F8023 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8023VLC | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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