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MC44011
7
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(continued)
(TA = 25
°
C, VCC1 = VCC2 = VCC3 = 5.0 V, unless otherwise noted.)
Characteristics
Unit
Max
Typ
Min
COLOR DIFFERENCE SECTION
Contrast (Gain)
Y1 to RGB (DAC $81 = 32, DAC $86 = 00)
Y2 to RGB (DAC $81 = 32, DAC $86 = 00)
Green In (Pin 27) to Green Out (Pin 21) with YX Enabled
($82–6 = 1, DAC $81 and DAC $86 = 32)
Red–to–Green and Blue–to–Green Gain Ratio
RGB Input to RGB Output with YX Not Enabled
($82–6 = 0, DAC $81 and DAC $86 = 32)
Ratio (DAC $81 = 00 versus 32)
Ratio (DAC $81 = 63 versus 32)
Red and Blue Trim Control (DACs $80, 82 varied from 00 to 63)
V/V
1.9
1.8
1.8
2.4
2.3
2.3
3.0
2.8
2.4
0.8
2.0
1.0
2.6
1.2
3.2
–
0.2
2.0
±
30
0.4
2.5
±
60
1.5
±
5.0
%
Saturation (Average of R, G, B saturation levels with respect to Luma)
Inputs at Pins 29 to 31 (DAC $86 = 32)
Ratio (DAC $86 = 00 versus 32)
Ratio (DAC $86 = 63 versus 32)
Inputs at Pins 26 to 28 (DAC $86 = 32, $82–6 = 1)
50
–
150
70
90
–
170
125
130
5
190
180
%
Brightness
Black Level Range (Brightness = 00 to 63 with respect to Brightness setting of 32)
Red and Blue Trim Control (DACs $83, 85 varied from 00 to 63)
±
0.3
±
0.05
±
0.5
±
0.3
±
0.7
±
0.6
Vdc
Color Coefficients
G–Y Matrix Coefficient versus B–Y
G–Y Matrix Coefficient versus R–Y
YX Matrix (Inputs at Pins 26 to 28, $82–6 = 1):
Y versus R
Y versus G
Y versus B
–0.21
–0.56
–0.19
–0.51
–0.17
–0.46
0.28
0.57
0.09
0.30
0.59
0.11
0.32
0.61
0.13
HORIZONTAL TIME BASE SECTION (PLL #1)
Free–Running Period (Calibration mode in effect, Bit $86–6 = 1)
17.7 MHz Crystal selected ($84–6 = 0)
14.3 MHz Crystal selected ($84–6 = 1)
62.5
62.5
64.0
63.5
65.5
65.5
μ
s
VCO minimum period (Pin 11 Voltage at 1.2 V)
VCO maximum period (Pin 11 Voltage at 2.8 V)
56
66
59.5
69.5
62
72
μ
s
VCO Control Gain factor
5.0
8.5
12
μ
s/V
Phase Detector Current
High Gain ($83–6 = 1)
Low Gain–to–High Gain Current Ratio
15
0.32
50
0.38
85
0.44
μ
A
μ
A/
μ
A
μ
s
Noise Gate Width ($77–2 = 0, Low Gain, see Figure 26)
–
16
–
Horizontal Filter Switch (Pin 12)
Saturation Voltage (I12 = 20
μ
A)
Dynamic Impendance ($84–7 = 1)
Parallel Resistance ($84–7 = 0)
–
–
10
100
–
–
mV
k
M
<5.0
1.0
0.6
Pins 8, 13, 14 Output Level
High (lO = –40
μ
A)
Low (lO = 800
μ
A)
2.4
–
4.5
0.1
–
Vdc
0.8
Burst Gate (Pin 8) Timing (See Figures 25, 27)
Rising edge from Sync leading edge (Pins 1, 3)
Rising edge from Sync center (Pins 26 to 29)
Pulse Width
μ
s
4.4
–
3.0
5.6
2.5
3.5
6.8
–
4.0
16Fh Output (Pin 13) Timing (Bit $85–6 = 0) (See Figures 25, 27)
Rising edge from Fh rising edge
Duty Cycle
–
–
1.3
50
–
–
μ
s
%
Composite Sync Output (Pin 13) Timing (Bit $85–6 = 1)
Input Sync center to Output Sync center (Pins 1, 3)
Input Sync center to Output Sync center (Pins 26 to 29)
μ
s
–
–
0.95
0.4
–
–