參數(shù)資料
型號： MC44011FB
廠商： MOTOROLA INC
元件分類： 消費家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 33/52頁
文件大小： 835K
代理商： MC44011FB
MC44011
33
MOTOROLA ANALOG IC DEVICE DATA
Write to Control Registers
Writing should be done only during vertical retrace. A write
cycle consists of three bytes (with three acknowledge bits):
1) The first byte is always the write address for the
MC44011 ($8A).
2) The second byte defines the sub–address register
(within the MC44011) to be operated on ($77 through
$88, and $00).
3) The third byte is the data for that register.
Communication begins when a start bit (data taken low
while clock is high), initiated by the master, is detected,
generating an internal reset. The first byte is then entered,
and if the address is correct ($8A), an acknowledge is
generated by the MC44011, which tells the master to
continue the communication. The second byte is then
entered, followed by an acknowledge. The third byte is the
operative data which is directed to the designated register,
followed by a third acknowledge.
Sub–Address Registers
The sub–addresses of the 19 registers are at $77
through $88, and $00. Fourteen of the registers use Bits
0–5 to operate DACs which provide the analog
adjustments. Most of the other bits are used to set/reset
functions, and to select appropriate inputs/outputs. Table 13
indicates the assignments of the registers.
Table 13. Sub–Address Register Assignments
Sub–
Address
7
6
5
4
3
2
1
0
$77
S–VHS Y
S–VHS C
FSI
L2 GATE
BLCP
L1 GATE
CBI
CAI
$78
36/38
μ
s
Cal Kill
(R–Y)/(B–Y) adjust DAC
$79
HI
VI
Subcarrier balance DAC
$7A
Xtal
SSD
$7B
T1
T2
$7C
SSC
SSA
$7D
P1
SSB
Blue bias for YUV operation DAC
$7E
P3
P2
Red bias for YUV operation DAC
$7F
D3
D1
Pixel Clock VCO Gain adjust DAC
$80
RGB EN
D2
Blue Contrast trim DAC
$81
Y2 EN
Y1 EN
Main Contrast DAC
$82
YUV EN
YX EN
Red Contrast trim DAC
$83
L2 Gain
L1 Gain
Blue Brightness trim DAC
$84
H Switch
525/625
Main Brightness DAC
$85
PClk/2
C Sync
Red Brightness trim DAC
$86
Vin Sync
Y2 Sync
PLL1 En
Main Saturation DAC (Color Difference section )
$87
0
(R–Y)/(B–Y) Saturation balance DAC (Decoder section)
$88
V2/V1
RGB Sync
Hue DAC
$00
Set to $00 to start Horizontal Loop if $88–6 = 0
Table 14 is a brief explanation of the individual control bits.
A more detailed explanation of the functions is found in the
block diagram description of the text (within the Functional
Description section). Table 15 provides an explanation of the
DACs. Each DAC is 6 bits wide, allowing 64 adjustment
steps. The proper sequence and control of the bits and
DACs, to achieve various system functions, is described in
the Applications Information section.
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