參數(shù)資料
型號(hào)： MC44011FB
廠商： MOTOROLA INC
元件分類： 消費(fèi)家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 30/52頁
文件大?。?/td> 835K
代理商： MC44011FB
MC44011
30
MOTOROLA ANALOG IC DEVICE DATA
3)
Sandcastle Output
(Pin 35) – This is a multilevel
output, at the horizontal frequency, used by the
MC44140 delay line. See the timing diagram of
Figures 25 and 27.
4)
16Fh/CSync
(Pin 13) – This is a dual purpose output,
TTL levels, user selectable. When Bit $85–6 is set to 0,
Pin 13 is a square wave at 16x the horizontal frequency
(250 kHz for PAL,
≈
252 kHz for NTSC). When Bit $85–6
is set to 1, Pin 13 is negative composite sync, derived
from the internal sync separator. See the timing diagram
of Figures 25 and 27.
The first three outputs mentioned above, and Pin 13 when
set to 16Fh, are consistent, and do not change duty cycle or
wave shape during the vertical sync interval. These four
outputs will also be present regardless of the presence of a
video signal at the selected input.
When Pin 13 is set to CSync output, it follows the incoming
composite sync format. If there is no video signal present at
the selected input, this output will be a steady logic high.
Loading on these pins should not be less than 2.0 k
to
either ground or 5.0 V.
Pin 11 is the filter for the PLL, and requires the
components shown in Figure 38, and with the values shown
in the application circuit of Figure 42. Pin 12 is a switch which
allows the filtering characteristics at Pin 11 to be changed.
Switching in the additional components (set $84–7 = 1)
increases the filter time constant, permitting better
performance in the presence of noisy signals.
The gain of the phase detector may be set high or low,
depending on the jitter content of the incoming horizontal
frequency, by using Bit $83–6. Broadcast signals usually
have a very stable horizontal frequency, in which case the
low gain setting ($83–6 = 0) should be used. When the video
source is, for example, a VCR, the high gain setting may be
preferable to minimize instability artifacts which may show up
on the screen.
The gating function ($77–2) provides additional control
where the stability of the incoming horizontal frequency is in
question. With this bit set to 0, gating is in effect, causing the
phase detector to not respond to the incoming sync pulses
during the vertical interval. This reduces disturbances in this
PLL due to the half–line pulses and their change in polarity.
The gating may be disabled by setting this bit to 1 where the
timing of the incoming sync is known to be stable. The gating
cannot be enabled if the phase detector gain is set high
($83–6 = 1).
Calibration Loop
The calibration loop (upper left portion of Figure 38)
maintains a near correct frequency of this PLL in the absence
of incoming sync signals. This feature minimizes
re–adjustment and lock time when sync signals are
re–applied. The calibration loop is similar to the PLL function,
receiving one frequency from the crystal (either 4.43 MHz or
3.58 MHz) divided down to a frequency similar to the
standard horizontal frequency. Bit $84–6 is used to set the
frequency divider to the correct ratio, depending on which
crystal is selected (see Table 9). The output of the frequency
comparator operates an up/down counter, which in turn sets
the D–to–A converter to drive the VCO through switch Sc.
The resulting frequency at the output of the divide–by–64
block is then fed to the frequency comparator to complete
the loop.
When a sync signal is not present at Phase Detector #1,
and at the Coincidence Detector, as indicated by the
coincidence detector’s output (Flag 12), Bit $78–6 should be
set to 0. This will cause the switch (Sc) to transfer to the
D–to–A converter for two lines (lines 4, 5) in each vertical
field, and will maintain the PLL1 at a frequency near the
standard horizontal frequency (between 14 to 16 kHz). When
lock to an incoming sync is established, Bit $78–6 may be set
to 1, disabling the periodic recalibration function, or it may be
left set to 0.
If a more accurate horizontal frequency is desired in the
absence of an input signal, Bit $86–6. can be set to 1 (and
Bit $84–6 set according to Table 9). This holds the horizontal
frequency to
≈
15.7 kHz. In this mode, Flag 12 will stay 0, as
the PLL will not be able to lock–up to a newly applied external
signal. To reset the system, set $86–6 to 0, write $00 to
register $00, and then check Flag 12 to determine when the
loop locks to an incoming signal.
Table 9. Calibration Loop
Crystal
Set Bit $84–6 to
14.3 MHz
1
17.7 MHz
0
On initial power up, Bit $86–6 (PLL1 EN) is automatically
set to 1, engaging the calibration loop continuously. This
condition will remain until this bit is set to 0, and $00 is written
to register $00, as part of the initialization routine.
Pixel Clock PLL (PLL2)
The second PLL, depicted in Figure 39, generates a high
frequency clock which is phase–locked to the horizontal
frequency.
Figure 39. Pixel Clock PLL (PLL2)
Phase and
Frequency
Comparator
Frequency
Divider
15625 Hz or
15750 Hz
fH from PLL1
Down
Up
15 k
Return
PLL2 Filter
Pixel
Clock
$85–7
2
VCO
Charge
Pump
L2 Gain
$83–7
VCO Gain
$7F–5/0
Voltage
Monitor
Flag 20 (VCO LO)
Flag 19 (VCO HI)
16
18
15
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