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參數(shù)資料
| 型號： | MC33976 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Dual Gauge Driver with Configurable Response Time(帶可設置響應時間的雙標尺驅(qū)動器) |
| 中文描述： | 雙計驅(qū)動器，可配置的響應時間（帶可設置響應時間的雙標尺驅(qū)動器） |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 5332K |
| 代理商： | MC33976 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
29
33976
FUNCTIONAL DEVICE OPERATION
STATE MACHINE
Internal Clock Calibration
Timing-related functions on the 33976 (e.g., pointer
velocities, acceleration, and Return To Zero Pointer speeds)
depend upon a precise, consistent time reference to control
the pointer accurately and reliably. Generating accurate time
references on an integrated circuit can be accomplished. For
example trimming can be used however, it tends to be costly
due to the large amount of die area required for trim pads.
Another possibility is an externally generated clock signal;
however, this requires a dedicated pin on the device and
controller. An alternate approach would require the use of an
additional crystal or resonator, which is expensive.
The internal clock in the 33976 is temperature
independent and area efficient; however, it can vary by up to
70 percent due to process variation. Using the existing SPI
inputs and the precision timing reference already available to
the microcontroller, the 33976 allows more accurate clock
calibration to within ±10 percent.
Calibrating the internal 1.0 MHz clock is initiated by writing
a logic [1] to PECCR bit PE3 (see
Figure 9
, page
30
). The
8.0
μ
s calibration pulse is then provided by the controller to
ideally result in an internal 33976 clock speed of 1.0 MHz.
The pulse is sent on the
CS
pin immediately after the SPI
word is sent. During the calibration, no other SPI lines should
be toggled. At the moment the
CS
pin transitions from
logic [1] to logic [0], an internal 7-bit counter counts the
number of cycles of an internal, 8.0 MHz clock. The counter
stops when the
CS
pin transitions from logic [0] to logic [1].
The value in the counter represents the number of cycles of
the 8.0 MHz clock occurring in the 8.0
μ
s window; it should
range from 32 to 119. An offset is added to this number to
help center or skew the calibrated result to generate a
desired maximum or nominal frequency. The modified
counter value is truncated by 4 bits to generate the calibration
divisor, which should range from 4 to 15. The 8.0 MHz clock
is divided by the calibration divisor, resulting in a calibrated
1.0 MHz clock. If the calibration divisor lies outside the range
of 4 to 15, the 33976 flags the CAL bit in the device status
register, indicating the calibration procedure was not
successful. A clock calibration is allowed only if the gauges
are disabled or the pointers are not moving, as indicated by
status bits MOV1 and MOV0 (
Table 20
, page
21
).
60
439
2277.9
136
273
3663.0
212
215
4651.2
61
434
2304.1
137
272
3676.5
213
215
4651.2
62
430
2325.6
138
271
3690.0
214
214
4672.9
63
426
2347.4
139
270
3703.7
215
214
4672.9
64
422
2369.7
140
269
3717.5
216
213
4694.8
65
418
2392.3
141
268
3731.3
217
212
4717.0
66
414
2415.5
142
267
3745.3
218
212
4717.0
67
410
2439.0
143
266
3759.4
219
211
4739.3
68
406
2463.1
144
265
3773.6
220
211
4739.3
69
403
2481.4
145
264
3787.9
221
210
4761.9
70
399
2506.3
146
263
3802.3
222
210
4761.9
71
396
2525.3
147
262
3816.8
223
209
4784.7
72
393
2544.5
148
261
3831.4
224
209
4784.7
73
389
2570.7
149
260
3846.2
225
208
4807.7
74
386
2590.7
150
259
3861.0
75
383
2611.0
151
258
3876.0
Table 30. Velocity Table (continued)
Velocity
Position
Time
Between
Steps (
μ
s)
Velocity
(
μ
Steps/s)
Velocity
Position
Time
Between
Steps (
μ
s)
Velocity
(
μ
Steps/s)
Velocity
Position
Time
Between
Steps (
μ
s)
Velocity
(
μ
Steps/s)
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