參數(shù)資料
型號： MC33976
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Dual Gauge Driver with Configurable Response Time(帶可設(shè)置響應(yīng)時間的雙標尺驅(qū)動器)
中文描述： 雙計驅(qū)動器，可配置的響應(yīng)時間（帶可設(shè)置響應(yīng)時間的雙標尺驅(qū)動器）
文件頁數(shù)： 15/40頁
文件大小： 5332K
代理商： MC33976
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
33976
FUNCTIONAL DEVICE OPERATION
COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS
PE8 (D8) — Pointer Position Gauge Select bit. Also the
Position 0 of the selected gauge is determined by the PE7
selection. This bit is recognized only if PE11 and PE10 = 1
and PE9 = 0.
0 = Gauge 0 position
1 = Gauge 1 position
PE7 (D7) — Position 0 Location Select bit. This bit
determines the Position 0 of the gauge selected by PE8. RTZ
direction will always be to the position 0.
0 = Position 0 is the most CCW (counterclockwise)
position
1 = Position 0 is the most CW (clockwise) position
PE6 (D6) — Motor Type Selection bit.
0 = MMT Style (coil phase difference = 90°)
1 = Switec Style (coil phase difference = 60°)
PE5 (D5) — Air Core Motor Emulation bit. This bit is
enabled or disabled (acceleration and deceleration is
constant if disabled).
0 = Enable
1 = Disable
PE4 (D4) — Clock Calibration Frequency Selector
0 = Maximum f =1.0 MHz (for 8.0
μ
s calibration pulse)
1 = Nominal f =1.0 MHz (for 8.0
μ
s calibration pulse)
PE3 (D3) — Clock Calibration Enable bit. This bit enables
or disables the clock calibration.
0 = Disable
1 = Enable
PE2 (D2) — Oscillator Adjustment
0 = t
CLU
1 = 0.66 x t
CLU
PE1 (D1) — Gauge 1 Enable bit. This bit enables or
disables the output driver of Gauge 1.
0 = Disable
1 = Enable
PE0 (D0) — Gauge 0 Enable bit. This bit enables or
disables the output driver of Gauge 0.
0 = Disable
1 = Enable
Address 001 — Maximum Velocity Register (VELR)
The Gauge Maximum Velocity Register is used to set a
maximum velocity for each gauge (refer to
Table 8
). Bits
V7:V0 contain a position value from 1– 225 that is
representative of the velocity position value described in
Table 30, Velocity Table
, page
27
. The table value becomes
the maximum velocity until it is changed to another value. If a
maximum value is chosen greater than the maximum velocity
in the acceleration table, the maximum table value becomes
the maximum velocity. If the motor is turning at a speed
greater than the new maximum, the motor immediately
moves down the velocity ramp until the speed falls equal to
or below it. Velocity for each motor can be changed
simultaneously or independently by writing V8 and/or V9 to a
logic [1]. Bits V12:V10 must be at logic [0] for valid VELR
commands.
The bits in
Table 8
are
write-only
.
V12:V10 (D12:D10) — These bits must be transmitted as
logic [0] for valid VELR commands
V9 (D9) — Gauge 1 Velocity. Specifies whether the
maximum velocity determined in the V7: V0 field will apply to
Gauge 1.
0 = Velocity does not apply to Gauge 1
1 = Velocity applies to Gauge 1
V8 (D8) — Gauge 0 Velocity. Specifies whether the
maximum velocity specified in the V7: V0 field will apply to
Gauge 0.
0 = Velocity does not apply to Gauge 0
1 = Velocity applies to Gauge 0
V7:V0 (D7:D0) — Maximum Velocity. Specifies the
maximum velocity position from
Table 30
, page
27
. This
velocity will remain the maximum of the intended gauge until
changed by command. Velocities can range from position 1
(00000001) to position 225 (11111111).
Addresses 010 and 011 — Gauge 0/1 Position Registers
(POS0R, POS1R)
SI Address 010 (Gauge 0 Position Register) and SI
Address 011 (Gauge 1 Position Register) Register bits PO
11: PO0 are written to when communicating the desired
pointer positions.
Commanded positions can range from 0 to 4095. The D12
bit is used to disable the damping (i.e., hold counts) for each
respective gauge. This feature allows the user to easily turn
on and off the damping that was configured with the
RMPSELR. Disabling the hold counts allows the pointer to
decelerate to the commanded position, as fast as possible
down the velocity ramp. When disabled, the acceleration and
deceleration of the pointer are symmetrical.
Table 8. Maximum Velocity Register (VELR)
Address 001
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
–
–
–
–
–
–
–
–
–
–
–
–
–
Write
0
0
0
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
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