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參數(shù)資料
| 型號： | MC145425DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ISDN Universal Digital Loop Transceivers II |
| 中文描述： | DATACOM, ISDN CONTROLLER, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 268K |
| 代理商： | MC145425DW |
MC145421
MC145425
MOTOROLA
9
In the master, time–out begins on the rising edge of the
third MSI following the last received burst. This is equivalent
to two MSI frames. The VD output is forced low during time–
out. The B channel output data will be unknown, but the
D channel bits will remain at their last values. Successful de-
modulation of a burst from the slave will result in leaving the
time–out state on the next rising MSI edge.
When the PD pin is used as an output on the slave UDLT,
time–out controls the pin. Time–out forces the PD output low
to indicate that the device has powered itself down. In this
case, the slave will not transmit to the master. However,
when a valid burst is received, time–out ends and the PD pin
is driven high to indicate power up. This feature allows the
slave UDLT to self–power–up and down in demand–powered
loop systems.
NOTE
The slave uses a free running clock during time–
out. After a long period without a burst from the
master, the timing between master and slave
could be such that more than one burst will be
needed to resync the two devices.
125
μ
s
1ST BIT
2ND BIT
1ST BIT
2ND BIT
B CHANNEL 1 OUTPUT
B CHANNEL 2 OUTPUT
B CHANNEL 2 INPUT
B CHANNEL 1 INPUT
HIGH–Z
MSI
VD
DCLK
D1I, D2I
D1O, D2O
TDC/RDC
TE1
TE2
RE1
RE2
Tx
Rx
DON’T CARE
Figure 1. Typical MC145421 Master ISDN UDLT Timing
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