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參數資料
| 型號： | MC145425DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | ISDN Universal Digital Loop Transceivers II |
| 中文描述： | DATACOM, ISDN CONTROLLER, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數： | 6/16頁 |
| 文件大?。?/td> | 268K |
| 代理商： | MC145425DW |
MC145421
MC145425
6
MOTOROLA
DCLK
D Channel Clock Input (Pin 8)
This input is the transmit and receive data clock for both
D channels. D channel input and output operation is de-
scribed in the D1O, D2O pin description.
Tx
Transmit Data Output (Pin 13)
This pin is high impedance when both TE1 and TE2 are
low. This pin serves as an output for B channel information
received from the slave device. The B channel data is under
the control of TE1, TE2, and TDC/RDC. (See TE1, TE2
description.)
Rx
Receive Data Input (Pin 21)
B channel data is input on this pin and is controlled by the
RE1, RE2, and TDC/RDC pins. (See RE1, RE2 description.)
TE1, TE2
Transmit Data Enable Input (Pins 14, 15)
These two pins control the output of data for their respec-
tive B channel on the Tx output pin. When both TE1 and TE2
are low, the Tx pin is high impedance. The rising edge of the
respective enable produces the first bit of the selected
B channel data on the Tx pin. Internal circuitry then scans for
the next negative transition of the TDC/RDC clock. Following
this event, the next seven bits of the selected B channel data
are output on the next seven rising edges of the TDC/RDC
data clock. When TE1 and TE2 are high simultaneously, data
on the Tx pin is undefined. TE1 and TE2 should be approxi-
mately leading–edge aligned with the TDC/RDC data clock
signal. In order to keep the Tx pin out of the high–impedance
state, these enable lines should be high while the respective
B channel data is being output.
RE1, RE2
Receive Data Enable Inputs (Pins 19, 20)
These inputs control the input of B channel data on the Rx
pin of the device. The rising edge of the respective enable
signal causes the device to load the selected receive data
buffer with data from the Rx pin on the next eight falling
edges of the TDC/RDC clock input. The RE1 and RE2
enables should be roughly leading–edge aligned with the
TDC/RDC data clock input. These enables are rising edge
sensitive and need not be high for the entire B channel input
period.
TDC/RDC
Transmit/Receive Data Clock Input (Pin 18)
This input is the transmit and receive data clock for the
B channel data. As described in the TE1/TE2 and the RE1/
RE2 sections, output data changes state on the rising edge
of this signal, and input data is read on the falling edges of
this signal. TDC/RDC should be roughly leading–edge
aligned with the TE1, TE2, RE1, and RE2 enables, as well as
the MSI frame reference signal.
MC145425 SLAVE PIN DESCRIPTIONS
VDD
Positive Supply (Pin 24)
The most positive power supply pin, normally + 5 V with
respect to VSS.
VSS
Negative Supply (Pin 1)
The most negative supply pin and logic ground, normally
0 V.
Vref
Reference Output (Analog Ground) (Pin 2)
This pin is the output of the internal reference supply and
should be bypassed to VDD and VSS with 0.1
μ
F capacitors.
This pin usually serves as an analog ground reference for
transformer coupling of the device’s incoming bursts from the
line. No external dc load should be placed on this pin.
LI
Line Input (Pin 3)
This pin is an input to the demodulator for the incoming
bursts. The input has an internal 240 k
resistor tied to the
Vref pin, an external capacitor or line transformer may be
used to couple the input signal to the device with no dc offset.
LO1, LO2
Line Driver Outputs (Pins 23, 22)
These push–pull outputs drive the twisted pair transmis-
sion line with a 512 kHz modified DPSK (MDPSK) burst each
125
μ
s; in other words at an 8 kHz frame rate. When not
modulating the line, these pins are driven to the active high
state — being the same potential, they create an ac short.
When used in conjunction with feed resistors, proper line ter-
mination is maintained.
CLK OUT
Clock Output (Pin 19)
This pin serves as a buffered output of the crystal fre-
quency divided by two. This clock is provided for systems
using the MC145428 Data Set Interface asynchronous/syn-
chronous terminal adaptor device.
LB
Loopback Control Input (Pin 4)
When this pin is low, the incoming B channels from the
master are burst back to the master — instead of the Rx B
channel input data. The B channel data from the master con-
tinues to be output at the slave’s Tx pin during loopback. If
the TONE and the loopback function are active simulta-
neously, the loopback function overrides the TONE function.
D channel data is not affected by LB.
VD
Valid Data Output (Pin 5)
A high on this pin indicates that a valid transmission burst
has been demodulated. A valid burst is determined by proper
synchronization and the absence of detected bit errors. If no
transmissions from the master have been received in the last
250
μ
s, as determined by an internal oscillator, VD will go
low.
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