- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369899 > MC145425DW (MOTOROLA INC) ISDN Universal Digital Loop Transceivers II PDF資料下載
參數(shù)資料
| 型號(hào)： | MC145425DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ISDN Universal Digital Loop Transceivers II |
| 中文描述： | DATACOM, ISDN CONTROLLER, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 268K |
| 代理商： | MC145425DW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
MC145421
MC145425
12
MOTOROLA
SWITCHING CHARACTERISTICS
(VDD = 5 V, TA = 0 to 70
°
C; CLoad= 50 pF)
No.*
Parameter
Min
Max
Unit
Master Timing
1
TDC/RDC Pulse Width High
110
—
ns
2
TDC/RDC Pulse Width Low
110
—
ns
3
MSI Rising Edge to TDC/RDC Falling Edge
90
—
ns
4
MSI Pulse Width
200
—
ns
5
MSI Rising Edge to First DCLK Falling Edge
90
—
ns
6
MSI Rising Edge to First D1O, D2O Bit Valid
—
100
ns
7
TE1, TE2 Rising Edge to TDC/RDC Falling Edge
110
—
ns
8
TDC/RDC Falling Edge to TE1, TE2 Rising Edge
20
—
ns
9
TE1, TE2 Rising Edge to First Tx Data Bit Valid
—
50
ns
10
TDC/RDC Rising Edge to Tx Data Bits 2 Through 8 Valid
—
50
ns
11
TE1, TE2 Falling Edge to Tx High–Impedance
—
70
ns
12
REI, RE2 Rising Edge to TDC/RDC Falling Edge
110
—
ns
13
TDC/RDC Falling Edge to RE1, RE2 Rising Edge
20
—
ns
14
Rx Data Setup (Data Valid Before TDC/RDC Falling Edge)
50
—
ns
15
Rx Data Hold (Data Valid After TDC/RDC Falling Edge)
20
—
ns
16
RE1, RE2 Pulse Width
220
—
ns
17
DCLK Rising Edge to D1O, D2O Bit Valid
—
135
ns
18
D1I, D2I Data Setup (Data Valid Before DCLK Falling Edge)
50
—
ns
19
D1I, D2I Data Hold (Data Valid After DCLK Falling Edge)
20
—
ns
20
DCLK Pulse Width Low
110
—
ns
21
DCLK Pulse Width High
110
—
ns
22
MSI Rising Edge to VD Valid
—
150
ns
23
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
50
—
ns
24
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
20
—
ns
Slave Timing
25
BCLK Pulse Width High (CCI = 8.192 MHz)
3.66
4.15
μ
s
μ
s
26
BCLK Pulse Width Low (CCI = 8.192 MHz)
3.66
4.15
27
EN1 or EN2 Rising Edge to BCLK Rising Edge
75
175
ns
28
EN1 or EN2 Rising Edge to DCLK Rising Edge
—
±
50
ns
29
EN1 or EN2 Rising Edge to First Tx Data Bit Valid
—
50
ns
30
BCLK Rising Edge to Tx Data Bits 2 Through 8 Valid
—
– 75
ns
31
DCLK Pulse Width High (CCI = 8.192 MHz)
31.0
31.5
μ
s
μ
s
32
DCLK Pulse Width Low (CCI = 8.192 MHz)
31.0
31.5
33
DCLK Rising Edge to D1O, D2O Bits Valid
—
50
ns
34
Rx Setup (Rx Data Valid Before BCLK Falling Edge)
175
—
ns
35
Rx Hold (Rx Data Valid After BCLK Falling Edge)
20
—
ns
36
D1I, D2I Setup (D1I, D2I Valid Before DCLK Falling Edge)
50
—
ns
37
D1I, D2I Hold (D1I, D2I Valid After DCLK Falling Edge)
20
—
ns
38
EN1 Rising Edge to VD Valid
—
50
ns
SE Pin Timing
39
LB, PD Hold (LB, PD Valid After SE Falling Edge)
20
—
ns
40
D1O, D2O, VD High Impedance After SE Falling Edge
—
70
ns
41
D1O, D2O, VD Valid After SE Rising Edge
60
—
ns
42
LB, PD Setup (LB, PD Valid Before SE Rising Edge)
50
—
ns
* See Switching Characteristics waveforms.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145425P | ISDN Universal Digital Loop Transceivers II |
| MC145421 | Universal Digital-Loop Transceiver2(通用數(shù)字回路收發(fā)器) |
| MC145425 | Universal Digital-Loop Transceiver2(通用數(shù)字回路收發(fā)器) |
| MC145428L | Data Set Interface Asynchronous-To-Synchronous Synchronous-To-Asynchronous Converter |
| MC145428P | Data Set Interface Asynchronous-To-Synchronous Synchronous-To-Asynchronous Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145425P | 制造商:Motorola Inc 功能描述: |
| MC145426P | 制造商:Motorola Inc 功能描述: |
| MC145428P | 制造商:Motorola Inc 功能描述: |
| MC145436ADW | 制造商:Motorola Inc 功能描述: |
| MC145436ADWR2 | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。