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參數(shù)資料
| 型號： | MC100EP222 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage ECL/PECL 1:15 Clock Driver(低壓ECL/PECL 1:15時鐘驅(qū)動器) |
| 中文描述： | 低壓ECL / PECL的一時15分時鐘驅(qū)動器（低壓ECL / PECL的一時15時鐘驅(qū)動器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 151K |
| 代理商： | MC100EP222 |
SEMICONDUCTOR TECHNICAL DATA
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from Timing Solutions Operation
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REV 0
Motorola, Inc. 2000
06/00
The MC100EP222 is a low voltage, low skew 1:15 differential %1 and %2
ECL/PECL clock distribution buffer. The MC100EP222 has been designed
and optimized for 2.5V and 3.3V systems. Target applications for this clock
driver are high performance clock distribution systems for computer,
networking and telecommunication systems.
Features:
15 differential ECL outputs (4 output banks)
2 selectable differential ECL inputs
Selectable 1:1 or 1:2 frequency outputs
150 ps device-to-device skew
50 ps pin-to-pin skew
Operates from a -2.5, -3.3V (ECL) or 2.5, 3.3V (PECL) power supply
Extended temperature operating range of -40 to +85 deg C
For information on thermal characteristics and its impact on operating life
time refer to AN1545, ”Thermal data for MPC clock drivers”
The MC100EP222 device characteristics allows low-skew clock
distribution of differential and single-ended LVECL/LVPECL signals. Typical
applications for the MC100EP222 are primary clock distribution systems on
backplanes of high-performance computer, networking and
telecommunication systems.
The MC100EP222 can be operated from a 3.3V or 2.5V positive supply (PECL mode) without the requirement of a negative
supply line. Each of the four output banks of two, three, four and six differential clock output pairs may be independently configured
to distribute the input frequency or %2 of the input frequency. The FSELA, FSELB, FSELC, FSELD and CLK_SEL are
asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the %2 outputs. For
the functionality of the MR control input, “Timing Diagram” on page 2.
Each of the CLK0, CLK1 inputs can be used differential of single-ended. For single-ended signals, connect the bypassed V
BB
output reference to the unused input of the pair.
The MC100EP222 guarantees low output-to-output skew of 50 ps and device-to-device skew of max. 150 ps. To ensure low
skew clock signals in the application, both sides of any differential output pair need to be terminated identically, even if only one
side is used. When fewer than all fifteen pairs are used, identical termination of all output pairs on the same package side is
recommended. If no outputs on a side are used, it is recommended to leave all of these outputs open and unterminated. This will
maintain minimum output skew.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
LOW VOLTAGE 3.3V/2.5V
1:15 DIFFERENTIAL ECL/PECL
CLOCK DRIVER
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D–03
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100EP223 | Low-Voltage 1:22 Differential PECL/HSTL Clock Driver(低壓1:22差分PECL/HSTL時鐘驅(qū)動器) |
| MC100H606FN | Registered Hex TTL/PECL Translator |
| MC10H606 | Registered Hex TTL/PECL Translator |
| MC10H606FN | Registered Hex TTL/PECL Translator |
| MC100H607FN | Registered Hex PECL/TTL Translator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP223 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP223TC | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP24D | 制造商:ON Semiconductor 功能描述: |
| MC100EP29 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset |
| MC100EP29DT | 功能描述:觸發(fā)器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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