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參數(shù)資料
| 型號： | MC100EP223 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low-Voltage 1:22 Differential PECL/HSTL Clock Driver(低壓1:22差分PECL/HSTL時鐘驅(qū)動器) |
| 中文描述： | 低電壓1時22分差分PECL / HSTL時鐘驅(qū)動器（低壓差分PECL的1點22 / HSTL時鐘驅(qū)動器） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 115K |
| 代理商： | MC100EP223 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1999
08/99
#! !
"
The MC100EP223 is a low skew 1–to–22 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The selected signal is fanned out to 22 identical differential
outputs.
200ps Part–to–Part Skew
50ps Output–to–Output Skew
Differential Design
Open Emitter HSTL Compatible Outputs
3.3V VCC
Both PECL and HSTL Inputs
75k
Input Pulldown Resistors
The EP223 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
The EP223 HSTL outputs are not realized in the conventional
manner. To minimize part–to–part and output–to–output skew, the HSTL
compatible output levels are generated with an open emitter
architecture. The outputs are pulled down with 50
to ground, rather
than the typical 50
to VDDQ pullup of a “standard” HSTL output.
Because the HSTL outputs are pulled to ground, the EP223 does not
utilize the VDDQ supply of the HSTL standard. The output levels are
derived from VCC.
In the case of an asynchronous control, there is a chance of
generating a ‘runt’ clock pulse when the device is enabled/disabled. To
avoid this, the output enable (OE) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50
, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In
the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW–VOLTAGE
1:22 DIFFERENTIAL
PECL/HSTL CLOCK DRIVER
FA SUFFIX
64–LEAD TQFP PACKAGE
CASE 840F–02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100H606FN | Registered Hex TTL/PECL Translator |
| MC10H606 | Registered Hex TTL/PECL Translator |
| MC10H606FN | Registered Hex TTL/PECL Translator |
| MC100H607FN | Registered Hex PECL/TTL Translator |
| MC10H607 | Registered Hex PECL/TTL Translator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP223TC | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP24D | 制造商:ON Semiconductor 功能描述: |
| MC100EP29 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset |
| MC100EP29DT | 功能描述:觸發(fā)器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP29DTG | 功能描述:觸發(fā)器 3.3V/5V ECL Dual Diff Data D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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