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參數(shù)資料
| 型號： | MB98A810Ax |
| 廠商： | Fujitsu Limited |
| 英文描述： | 1M Flash Eelectrically Erasable and Programmable (Flash) memory cards(1M電可擦除可編程閃速存儲器卡) |
| 中文描述： | 100萬閃光Eelectrically可擦除和可編程（閃存）記憶卡（1分電可擦除可編程閃速存儲器卡） |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 353K |
| 代理商： | MB98A810AX |
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MB98A808Ax-20
MB98A809Ax-20
MB98A810Ax-20
MB98A811Ax-20
10
COMMAND DEFINITION TABLE
Command Table for 8-bit Mode
Write
Read Intelligent ID Codes
*
4
Second Bus Cycle
Operation
*
1
Address
*
2
Data
*
3
First Bus Cycle
Address
*
2
Operation
*
1
Data
*
3
Write
Write
Write
Write
Write
Write
Read
Write
Write
Read
Write
00H
90H
20H
A0H
40H
CH
FFH
ZA
WA
WA
ZA
WA
WA
20H
EVD
WD
WVD
FFH
Bus Cycle
Required
Read Memory
Set Up Erase / Erase
*
5
Erase Verify *5
Set Up Write / Write
*
6
Write Verify
*
6
Command
Reset *7 *8
1
3
2
2
2
2
2
RA
IA
ZA
EA
ZA
EA
Read
ID
IA
—
—
—
Command Table for 16-bit Mode
Write
Read Intelligent ID Codes
*
4
Second Bus Cycle
Operation
*
1
Address
*
2
Data
*
3
First Bus Cycle
Address
*
2
Operation
*
1
Data
*
3
Write
Write
Write
Write
Write
Write
Read
Write
Write
Write
0000H
9090H
2020H
A0A0H
4040H
C0C0H
FFFFH
ZA
WA
WA
ZA
WA
WA
2020H
EVD
WD
WVD
FFFFH
Bus Cycle
Required
Read Memory
Set Up Erase / Erase
*
5
Erase Verify *5
Command
Reset *7 *8
1
3
2
2
2
2
2
RA
IA
ZA
EA
ZA
EA
Set Up Write / Write
*
6
Write Verify
*
6
Read
Read
—
—
—
IA
ID
Notes:
*
1 Bus operations are defined in “FUNCTION TRUTH TABLE”.
*
2 IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Address of memory location to be read during erase verify.
RA = Read Address
WA = Address of memory location to be written.
ZA = Address of 128K-Byte zones involved in erase operation.
Addresses are latched on the falling edge of the Write Enable pulse.
*
3 ID = Data read from location IA during device identification.
Manufacturer = 31H for 8-bit, 3131H for 16-bit / Device = B4H for 8-bit, B4B4H for 16-bit
EVD = Data read from location EA during erase verify.
WD = Data to be programmed at location WA. Data is latched on the rising edge of Write Enable.
WVD = Data read from location WA during write verify. WA is latched on the Write command.
*
4 Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
*
5 “ERASE FLOWCHART” in Fig.6, Fig.7 and Fig.8 illustrate the Erase Algorithm.
*
6 “WRITE FLOWCHART” in Fig.4 and Fig.5 illustrate the Write Algorithm.
*7 The second bus cycle must be followed by the desired command register write.
*8 The Reset command operates on a zone basis. To reset the entire card requires reset write cycles to each zone.
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