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參數(shù)資料
| 型號： | MB91F464AA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 67/67頁 |
| 文件大?。?/td> | 486K |
| 代理商： | MB91F464AA |
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European MCU Design Centre
MB91F464AA preliminary datasheet ver. 1.11
Page 9 of 67
2.2.2 FR70 CPU Core
32-bit RISC, load/store architecture, pipeline 5 stages
Maximum operating frequency: Core clock = 64 MHz to 100 MHz (device dependent)
(Source oscillation= 4 MHz, multiplied by 16 to 25 (PLL clock multiplier method))
General-purpose registers: 16 x 32 bits
16-bit fixed-length instruction (Base instruction)
32-bit linear address space: 4 Gbytes
Instructions suitable for embedded application
Transfer command between memories
Bit-processing instruction
Barrel-shift instructions
Instructions supporting C-language
Function's enter command /exit command
Multi-load/store command of register contents
Assembler statement is also easily available
Register's interlock function
Multiplier's embedded application/command level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS are saved): 6 cycles (16 priority level)
Harvard architecture enables simultaneous execution of program access and data access
Memory protection function
Embedded debug support
Commands compatible with FR family
2.2.3 Instruction Cache
I-Cache is not available on MB91F464AA.
2.2.4 Interrupt Controller
A total of 10 external interrupt lines ( 8 normal interrupt pins, 2 interrupt pins shared with
peripheral inputs for Wake Up from STOP mode (CAN RX and I
2C SDA)
Interrupts from internal peripherals (128 interrupt vectors)
Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16
levels)
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