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參數(shù)資料
| 型號(hào)： | MB91F464AA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 11/67頁 |
| 文件大?。?/td> | 486K |
| 代理商： | MB91F464AA |
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European MCU Design Centre
MB91F464AA preliminary datasheet ver. 1.11
Page 19 of 67
2.4.3.2
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash
memory's interface circuit enables direct control of the Flash memory unit from external pins by
directly linking some of the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is
generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of
the 16.5 Mbit Flash memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F464AA external pins
MBM29LV400TC
External pins
FR-CPU mode
Flash memory
mode
Normal function
Pin number
Comment
-
INITX
-
INITX
52
RESET
-
FRSTX
GP16_7
53
-
MD2
99
Set to ‘1’
-
MD1
98
Set to ‘1’
-
MD0
92
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
GP24_0
74
BYTE
Internally fixed to
‘H’
BYTEX
GP24_2
78
WE
WEX
GP28_3
29
OE
OEX
GP28_2
28
CE
CEX
GP28_1
27
-
ATDIN
GP22_1
73
Set to ‘0’
-
EQIN
GP22_0
72
Set to ‘0’
-
TESTX
GP24_3
79
Set to ‘1’
-
Internal control
signal + control
via interface
circuit
RDYI
GP24_1
77
Set to ‘0’
A0
FA0
GP19_2
47
Set to ‘0’
A1 to A8
FA1 to FA8
GP27_0 to
GP27_7
16 to 23
A9 to A16
FA9 to FA16
GP15_0 to
GP15_5,
GP21_0, GP21_1
68 to 71,
10, 11,
57, 58
A17 to A19
FA17 to FA19
GP21_2,
GP21_4,
GP21_5
59, 60, 61
A20 to A21
Internal address
bus
FA20, FA21
GP21_6, GP28_0
62, 24
Set to ‘1’
DQ0 to DQ7
GP17_0 to
GP17_7
48, 49, 54, 55,
56, 65, 66, 67
DQ8 to DQ15
Internal data bus
DQ8 to DQ15
GP14_0 to
GP14_7
2 to 9
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| MB91F464ABPMCR-GSE2 | 制造商:FUJITSU 功能描述:MCU 32BIT FR 416K FLASH 100LQFP |
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