參數(shù)資料
型號: MB91F464AA
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 5/67頁
文件大?。?/td> 486K
代理商: MB91F464AA
European MCU Design Centre
MB91F464AA preliminary datasheet ver. 1.11
Page 13 of 67
SPI compatible
LIN master and slave
LIN-USART 0 and ICU 0 co-operate (for LIN sync field in slave mode)
LIN-USART 1 and ICU 1 co-operate (for LIN sync field in slave mode)
LIN-USART 2 and ICU 2 co-operate (for LIN sync field in slave mode)
LIN USART 3 and ICU 3 co-operate (for LIN sync field in slave mode)
LIN USART 4 and ICU 4 co-operate (for LIN sync field in slave mode)
CAN : 1 channel
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (cocatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
I
2C (400k fast mode) : 1 channel
Master or slave transmission
Arbitration function
Clock synchronization function
Slave address and general call address detect function
Transfer direction detect function
Start condition repeat generation and detection function
Bus error detect function
Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit
addressing)
Includes clock divider functionality
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of
spikes in the range of 1 to 1.5 cycles of the Peripheral Clock.
Stepper Motor Controller : 0 channels
There are no Stepper Motor Controllers on MB91F464AA.
Timebase/watchdog timer (26 bits)
Adjustable watchdog timer interval (between 2
20 and 226 system clock cycles)
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