參數(shù)資料
型號(hào): MB91F463NCPMC-GSE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, LQFP-64
文件頁數(shù): 16/84頁
文件大?。?/td> 1954K
代理商: MB91F463NCPMC-GSE1
MB91460N Series
DS07-16607-4E
23
2.
Internal architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of
each other.
A 32-bit
16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU
and peripheral resources.
A Harvard
Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
The following figure shows the internal architecture structure.
R-bus
16
I-bus
32
D-bus
32
Instruction
RAM
2 Kbytes
32
16
bus adapter
CAN
2 channels
Bus converter
DMAC
5 channels
Bit search
Data RAM
8 Kbytes
FR60 CPU
core
Peripheral
resource
Flash memory
288 Kbytes
Flash-instruction
cache
4 Kbytes
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