參數(shù)資料
型號(hào)： MB91F361G
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 64 MHz, MICROCONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 19/54頁
文件大小： 675K
代理商： MB91F361G
FME / EMDC / Br
mb91f361g.fm
26
7/19/00
1) this is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at volt-
ages less or equal than 4.5 V (see spec items for power-down reset)
2) valid for bidirectional tristate I/O PAD cell
3) these are preliminary values from first evaluation. Min/Max are from test spec, typ is measured by tester
with 2 samples in July 2000.
7.3
Clock Settings
Note: If the maximum frequency of 64 MHz is set for CLKB it is not allowed to have an odd division factor for CLKT
(3, 5, 7, 9, 11, 13, 15 are not allowed as dividers for CLKT).
I2C Bus Interface
- Output voltage
- Output current
VoutHIGH
VoutLOW
Iout
VSS
3
VDD
VSS+0.4
V
mA
Open Drain Output
IoutLOW= 3mA
Lock-up time PLL1
(4MHz->16…64MHz)
1ms
ESD Protection
(Human body model MIL883-B
compliant)
Vsurge
2kV
Rdischarge=1.5k
Cdischarge= 100pF
Clock
domain
Clock name
Max.
frequency
setting
Remark
Core
CLKB
64 MHz
see note below table
Resource
bus
CLKP
32 MHz
Ext. Bus
CLKT
32 MHz
For access to the ash memory 1 wait cycles is nec-
essary is this case;
see also note below table
相關(guān)PDF資料
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