參數(shù)資料
型號(hào)： MB91F361G
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 64 MHz, MICROCONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 14/54頁(yè)
文件大?。?/td> 675K
代理商： MB91F361G
FME / EMDC / Br mb91f361g.fm
21
7/19/00
4
Power-on sequence
All VDD pins should be connected to the same potential (exception see chapter 1). The analogue supply voltage
(AVCC) must not be turned on before the digital supply voltage. If the external bus interface is supplied with 3.3 V
as described in chapter 1 this voltage also must not be turned on before the 5V digital voltage has been switched
on. If the supply voltage to the external bus interface is switched off (it may not be tristate but should be pulled low)
it must be made sure that all related signals do not have a voltage higher than this pulled down supply.
Immediately after power on always execute INIT at the INITX pin (input a low level to the INITX pin). Hold this low
level at the INITX pin long enough so that after release of the low level at INITX and the passing of the built in
waiting time stable oscillation of the oscillation circuit is achieved. INITX must be pulled low for at least 8 cycles of
the 4 MHz oscillation clock.
5
Handling of Unused Input Pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the de-
vice. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more
than 2 KOhm.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at the
unused pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up
will flow through those diodes.
6
Emulation Device
6.1
Overview
MB91V360 can be used as emulation device for MB91F361G. However, the differences described below have to
be taken into account. A new emulation device MB91FV360G which will allow emulation of all features is under
developement.
MB91F361G does not include CAN3 of MB91V360/MB91FV360G
MB91F361G has 4 KB of RAM at the F-bus as compared to 16 KB on MB91V360/MB91FV360G.
MB91F361G has an instruction cache of 1 kB (on MB91V360/MB91FV360G it is 4 KB cache).
MB91F361G and MB91FV360G contain an additional I2C module which can operate at I2C bus frequencies up to
400 kHz (fast mode) and allows 10 bit addressing. Either the original module as implemented on MB91V360 or the
new one can be used.
On MB91F361G and MB91FV360G the pads for the I2C Interface do not include internal pull-up resistors any
more.
The outputs of the stepper motor controllers on MB91F361G and MB91FV360G now have an improved EMC be-
havior (longer slew rates).
For some more details about additional differences see the chapters below.
相關(guān)PDF資料
PDF描述
MB91F368GA 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP120
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