
MB91605 Series
17
■ HANDLING DEVICES
Preventing latch-up
Latch-up may occur in a CMOS IC if a voltage higher than VDDE or VDDI, or less than VSS is applied to an input or
output pin or if a voltage exceeding the rated value is applied between VDDE and VSS, or VDDI and VSS. If
latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
Handling of unused input pins
If unused input pins are left open, malfunctions may result. Any unused input pins should be connected to a pull-
up or pull-down resistor.
Power supply pins
The MB91605 series has multiple VDDE, VDDI, and VSS pins. respective pins at the same potential are intercon-
nected in order to prevent latch-up and other malfunctions. However, you must connect the pins externally to the
power supply and ground lines to reduce the electro-magnetic emission levels, to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Furthermore,
the VDDE pins, VDDI pins and VSS pins of the MB91605 series must be connected to the current supply source
at a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1
F as a bypass capacitor between
the VDDE, VDDI and VSS pins near the device.
Crystal oscillator circuit
Noise in proximity to the X0 and X1 pins can cause the device to malfunction. Printed circuit boards should be
designed so that the X0 and X1 pins, crystal oscillator, and bypass capacitors connected to ground are located
near the device and ground.
It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins are surrounded
by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
Mode pins (MD0, MD1)
Connect them directly to power supply pins or GND pins. To prevent the device from entering test mode acci-
dentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or
GND pin on the printed circuit board as much as possible and connect them at a low impedance.
Operation at power-on
Ensure that a settings initialization reset (INIT) is performed using the INIT pin immediately after the power is
turned on.
Maintain the “L” level input to the INIT pin for the duration of the stabilization wait time immediately after the
power on to ensure the stabilization wait time as required by the oscillator circuit (the stabilization wait time is
reset to the minimum value when INIT is asserted using the INIT pin).
Note on oscillator input at power-on
At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed.